This course provides an introduction to the analysis and design of digital systems and microprocessors. Review of combinational analysis and design. Analysis and design of synchronous finite state machines and register transfer level systems. Computer aided design and programming of digital electronic circuits through the application of several modern software packages. A detailed introduction to VERILOG hardware description language. Extensive hardware labs involving the implementation of complex digital systems in FPGA programmable logic devices. Microprocessor devices, their architecture and instruction sets. Hardware aspects of instruction execution. Assembly language and C programming. Input/output, bus interfacing, interrupts. Co-design of digital hardware and microprocessor systems.
Learning Outcomes
Upon successful completion, students will have the knowledge and skills to:
1. Design combinational and sequential logic hardware using schematics and Verilog HDL. Follow an appropriate workflow for digital system design tasks and their implementation in programmable logic.2. Analyse and design complex digital systems through the Finite State Machine and Register-Transfer-Level frameworks.
3. Demonstrate a solid understanding of basic C and Assembly programming languages in an embedded programming context.
4. Describe the architecture, programming and use of microprocessors and FPGAs, and distinguish appropriate areas of application for each technology.
5. Adopt a top-down design approach to deconstruct a design goal and translate system requirements into a practical design.
6. Plan, execute and report on a project working in a group.
7. Use a number of commercial and open-source softwares: ISE WebPACK, ICARUS Verilog, GTKwave, Atmel Studio.
8. Demonstrate practical electronics testbench skills and use a development board.
9. Interpret schematics and datasheets.
10. Communicate effectively in written form about their work.
Professional Skills Mapping:
Mapping of Learning Outcomes to Assessment and Professional Competencies
The ANU uses Turnitin to enhance student citation and referencing techniques, and to assess assignment submissions as a component of the University's approach to managing Academic Integrity. While the use of Turnitin is not mandatory, the ANU highly recommends Turnitin is used by both teaching staff and students. For additional information regarding Turnitin please visit the ANU Online website.
Requisite and Incompatibility
Majors
Minors
Fees
Tuition fees are for the academic year indicated at the top of the page.
If you are a domestic graduate coursework or international student you will be required to pay tuition fees. Tuition fees are indexed annually. Further information for domestic and international students about tuition and other fees can be found at Fees.
- Student Contribution Band:
- 2
- Unit value:
- 6 units
If you are an undergraduate student and have been offered a Commonwealth supported place, your fees are set by the Australian Government for each course. At ANU 1 EFTSL is 48 units (normally 8 x 6-unit courses). You can find your student contribution amount for each course at Fees. Where there is a unit range displayed for this course, not all unit options below may be available.
| Units | EFTSL |
|---|---|
| 6.00 | 0.12500 |
Course fees
- Domestic fee paying students
| Year | Fee |
|---|---|
| 2015 | $3096 |
- International fee paying students
| Year | Fee |
|---|---|
| 2015 | $4146 |
Offerings, Dates and Class Summary Links
ANU utilises MyTimetable to enable students to view the timetable for their enrolled courses, browse, then self-allocate to small teaching activities / tutorials so they can better plan their time. Find out more on the Timetable webpage.
Class summaries, if available, can be accessed by clicking on the View link for the relevant class number.
First Semester
| Class number | Class start date | Last day to enrol | Census date | Class end date | Mode Of Delivery | Class Summary |
|---|---|---|---|---|---|---|
| 1947 | 16 Feb 2015 | 06 Mar 2015 | 31 Mar 2015 | 29 May 2015 | In Person | N/A |