• Class Number 7609
  • Term Code 3260
  • Class Info
  • Unit Value 6 units
  • Topic Computer Microarchitecture
  • Mode of Delivery In Person
  • COURSE CONVENER
    • Shoaib Akram
  • LECTURER
    • Shoaib Akram
  • Class Dates
  • Class Start Date 25/07/2022
  • Class End Date 28/10/2022
  • Census Date 31/08/2022
  • Last Date to Enrol 01/08/2022
  • TUTOR
    • David Quarel
    • Nicholas Miehlbradt
    • Benjamin Gray
    • Harris Loi
SELT Survey Results

This course is available so that senior students can pursue, with a small class, topics that are not covered in the regular curriculum that will significantly increase their knowledge of some aspect of computer science.

The activities in the course will be a combination of lectures, workshops, reading, writing and project work, as appropriate to the topic. These activities will be specified in separate websites for each class.

Learning Outcomes

Upon successful completion, students will have the knowledge and skills to:

  1. Learning Outcomes will be determined for each individual student and recorded in an 'Independent Study Contract' at the beginning of the course.

Required Resources

Digital Design and Computer Architecture: ARM Edition by David Harris and Sarah L. Harris, Morgan Kaufmann, ISBN-13: 978-0-12-800056-4 (free at https://dl.acm.org/doi/10.5555/2815529).


The C Programming Language by Brian Kernighan and Dennis Ritchie, Prentice Hall Professional Technical Reference, ISBN-13: 978-0-13-110370-2.

Whether you are on campus or studying remotely, there are a variety of online platforms you will use to participate in your study program. These could include videos for lectures and other instruction, two-way video conferencing for interactive learning, email and other messaging tools for communication, interactive web apps for formative and collaborative activities, print and/or photo/scan for handwritten work and drawings, and home-based assessment.

ANU outlines recommended student system requirements to ensure you are able to participate fully in your learning. Other information is also available about the various Learning Platforms you may use.

Staff Feedback

Students will be given feedback in the following forms in this course:

  • written comments
  • verbal comments
  • feedback to whole class, groups, individuals, focus group etc

Student Feedback

ANU is committed to the demonstration of educational excellence and regularly seeks feedback from students. Students are encouraged to offer feedback directly to their Course Convener or through their College and Course representatives (if applicable). Feedback can also be provided to Course Conveners and teachers via the Student Experience of Learning & Teaching (SELT) feedback program. SELT surveys are confidential and also provide the Colleges and ANU Executive with opportunities to recognise excellent teaching, and opportunities for improvement.

Class Schedule

Week/Session Summary of Activities Assessment
1 Semiconductor technology trends and introduction to microarchitecture. Sources of complexity in modern processors. Energy and security implications of microarchitectural state. Review of digital logic basics. Introduction to Instruction-Level Parallelism (ILP).
2 Fundamentals of Instruction Set Architectures (ISAs). A look into key differences between RISC and CISC ISAs. Laying down the key principles of robust ISA design. How does ISA design introduce a tension between the processor microarchitecture and the programming model? CPU design project (1) is released; Paper review assignment is released
3 Single-cycle processor design. Design and implementation of datapath and control unit. Designing a simple in-order processor pipeline. Understanding the key limitations of in-order pipelines.
4 Understanding and mitigating data and control hazards in in-order pipelines. Implementing forwarding and hazard detection in an in-order pipeline. Motivation for branch prediction and introduction to simple branch predictors.
5 A tour of several modern branch predictors. Evolution of branch prediction over the last many decades. Multiscalar execution. Exception handling.
6 Out-of-order pipelining. Microarchitecture of the Control Data Corporation (CDC) 6600 and IBM 360/90 computers. Tomasulo algorithm for out-of-order processors. Motivation for (and implementation of) register renaming, dynamic scheduling and hardware speculation. Reorder buffer-based Intel and AMD processors. CPU design project (1) is due; Homework 1 is released
7 Limitations of reorder buffer design for out-of-order processors. Introduction to physical register file (PRF) for building out-of-order processors. Microarchitecture of the Intel Sandy Bridge and newer processors. Homework 1 is due
8 Enhancing processor speed with speculative load/store execution. Security implications of speculation. Superscalar pipelines. Complexity effective processor design. Instruction scheduling basics and the select-wakeup loop case study. CPU design project (2) is released
9 Introduction to modern cache hierarchies, including direct-mapped and set-associative caches. Cache replacement policies. Writeback and write-through caching. Non-temporal stores. Efficient circuits for set-associative caches.
10 Advanced optimizations for modern cache hierarchies. Victim cache. Way prediction. Miss status handling register. Multi-level inclusion. Memory Level Parallelism (MLP) fundamentals. Performance analysis of multi-level caches.
11 Virtual memory and its interaction with cache hierarchies. Cache indexing in the presence of virtual memory. Dealing with synonyms in virtually indexed caches. Translation look aside buffer. Software and hardware support for virtual memory and page fault handling. CPU design project (2) is due
12 Design and organization of main memory. DRAM cell and module design and organization. Limitations of DRAM technology. Motivation for persistent memory and NVMe storage. Paper review assignment is due

Tutorial Registration

Tutorial registration will be via an online system (e.g., FAIS/Streams).

Assessment Summary

Assessment task Value Learning Outcomes
Processor Design with a Logic Simulator 20 % 1
Processor Component Design with an Architectural Simulator 20 % 1
Final Exam 12 % 1
Homework 1 8 % 1
Paper Review 40 % 1

* If the Due Date and Return of Assessment date are blank, see the Assessment Tab for specific Assessment Task details

Policies

ANU has educational policies, procedures and guidelines , which are designed to ensure that staff and students are aware of the University’s academic standards, and implement them. Students are expected to have read the Academic Integrity Rule before the commencement of their course. Other key policies and guidelines include:

Assessment Requirements

The ANU is using Turnitin to enhance student citation and referencing techniques, and to assess assignment submissions as a component of the University's approach to managing Academic Integrity. For additional information regarding Turnitin please visit the Academic Skills website. In rare cases where online submission using Turnitin software is not technically possible; or where not using Turnitin software has been justified by the Course Convener and approved by the Associate Dean (Education) on the basis of the teaching model being employed; students shall submit assessment online via ‘Wattle’ outside of Turnitin, or failing that in hard copy, or through a combination of submission methods as approved by the Associate Dean (Education). The submission method is detailed below.

Moderation of Assessment

Marks that are allocated during Semester are to be considered provisional until formalised by the College examiners meeting at the end of each Semester. If appropriate, some moderation of marks might be applied prior to final results being released.

Participation

The assessments in this course demand hands-on training. Without attending tutorials and submitting and testing the laboratory exercises every week, the students will find it extremely hard to finish the assignments. Therefore, we expect high participation in the tutorials. Each lecture will offer an in-class quiz which will prepare students for the final exam. Therefore, attending the lectures and participating in the discussions and solving the quiz questions is extremely important.

Examination(s)

There will be a final exam worth 40%. The exam will cover the course content covered in lectures in the first eleven weeks.

Assessment Task 1

Value: 20 %
Learning Outcomes: 1

Processor Design with a Logic Simulator

The first assignment in this course requires designing and building a working processor in a logic simulator. The students will be provided hands-on training with the use of the required tools. The students will be provided with a specification of the instruction set architecture.

Assessment Task 2

Value: 20 %
Learning Outcomes: 1

Processor Component Design with an Architectural Simulator

The second assignment in this course requires students to build a specific processor component (e.g., branch predictor or prefetcher) in a modern architectural simulator. This assignment requires working with the C++ programming language.

Assessment Task 3

Value: 12 %
Learning Outcomes: 1

Final Exam

There is only one examination in this course. The final exam will be held during the exam period.

Assessment Task 4

Value: 8 %
Learning Outcomes: 1

Homework 1

The homework covers the content covered during the first six weeks. The homework questions will ask students to creatively implement new processor ideas in a limited context.

Assessment Task 5

Value: 40 %
Learning Outcomes: 1

Paper Review

Students will pick one top-tier paper from a computer architecture conference and write a critical review.

Academic Integrity

Academic integrity is a core part of the ANU culture as a community of scholars. The University’s students are an integral part of that community. The academic integrity principle commits all students to engage in academic work in ways that are consistent with, and actively support, academic integrity, and to uphold this commitment by behaving honestly, responsibly and ethically, and with respect and fairness, in scholarly practice.


The University expects all staff and students to be familiar with the academic integrity principle, the Academic Integrity Rule 2021, the Policy: Student Academic Integrity and Procedure: Student Academic Integrity, and to uphold high standards of academic integrity to ensure the quality and value of our qualifications.


The Academic Integrity Rule 2021 is a legal document that the University uses to promote academic integrity, and manage breaches of the academic integrity principle. The Policy and Procedure support the Rule by outlining overarching principles, responsibilities and processes. The Academic Integrity Rule 2021 commences on 1 December 2021 and applies to courses commencing on or after that date, as well as to research conduct occurring on or after that date. Prior to this, the Academic Misconduct Rule 2015 applies.

 

The University commits to assisting all students to understand how to engage in academic work in ways that are consistent with, and actively support academic integrity. All coursework students must complete the online Academic Integrity Module (Epigeum), and Higher Degree Research (HDR) students are required to complete research integrity training. The Academic Integrity website provides information about services available to assist students with their assignments, examinations and other learning activities, as well as understanding and upholding academic integrity.

Online Submission

The assignment submission will be through the teaching Gitlab. You will be required to electronically sign a declaration as part of the submission of your assignment. Please keep a copy of the assignment for your records.

Hardcopy Submission

The two assignment submissions in this course will be soft copy submissions. We are aiming for in person (paper) exams. We will adjust the policy as per circumstances.

Late Submission

Individual assessment tasks may or may not allow for late submission. Policy regarding late submission is detailed below:

  • Late submission not permitted. If submission of assessment tasks without an extension after the due date is not permitted, a mark of 0 will be awarded.

Referencing Requirements

The Academic Skills website has information to assist you with your writing and assessments. The website includes information about Academic Integrity including referencing requirements for different disciplines. There is also information on Plagiarism and different ways to use source material.

Extensions and Penalties

Extensions and late submission of assessment pieces are covered by the Student Assessment (Coursework) Policy and Procedure. Extensions may be granted for assessment pieces that are not examinations or take-home examinations. If you need an extension, you must request an extension in writing on or before the due date. If you have documented and appropriate medical evidence that demonstrates you were not able to request an extension on or before the due date, you may be able to request it after the due date.

Privacy Notice

The ANU has made a number of third party, online, databases available for students to use. Use of each online database is conditional on student end users first agreeing to the database licensor’s terms of service and/or privacy policy. Students should read these carefully. In some cases student end users will be required to register an account with the database licensor and submit personal information, including their: first name; last name; ANU email address; and other information.
In cases where student end users are asked to submit ‘content’ to a database, such as an assignment or short answers, the database licensor may only use the student’s ‘content’ in accordance with the terms of service – including any (copyright) licence the student grants to the database licensor. Any personal information or content a student submits may be stored by the licensor, potentially offshore, and will be used to process the database service in accordance with the licensors terms of service and/or privacy policy.
If any student chooses not to agree to the database licensor’s terms of service or privacy policy, the student will not be able to access and use the database. In these circumstances students should contact their lecturer to enquire about alternative arrangements that are available.

Distribution of grades policy

Academic Quality Assurance Committee monitors the performance of students, including attrition, further study and employment rates and grade distribution, and College reports on quality assurance processes for assessment activities, including alignment with national and international disciplinary and interdisciplinary standards, as well as qualification type learning outcomes.

Since first semester 1994, ANU uses a grading scale for all courses. This grading scale is used by all academic areas of the University.

Support for students

The University offers students support through several different services. You may contact the services listed below directly or seek advice from your Course Convener, Student Administrators, or your College and Course representatives (if applicable).

Shoaib Akram
U1093210@anu.edu.au

Research Interests


Computer Systems. Memory and storage systems.

Shoaib Akram

Shoaib Akram
shoaib.akram@anu.edu.au

Research Interests


Shoaib Akram

David Quarel
u5354853@anu.edu.au

Research Interests


David Quarel

Nicholas Miehlbradt
u6409116@anu.edu.au

Research Interests


Nicholas Miehlbradt

Benjamin Gray
u6677379@anu.edu.au

Research Interests


Benjamin Gray

Harris Loi
u6688826@anu.edu.au

Research Interests


Harris Loi

Responsible Officer: Registrar, Student Administration / Page Contact: Website Administrator / Frequently Asked Questions