• Class Number 2364
  • Term Code 3330
  • Class Info
  • Unit Value 6 units
  • Mode of Delivery In Person
    • AsPr Nan Yang
    • Hanwen Bi
    • Dr Xiangyun Zhou
    • Jiarui Wang
  • Class Dates
  • Class Start Date 20/02/2023
  • Class End Date 26/05/2023
  • Census Date 31/03/2023
  • Last Date to Enrol 27/02/2023
    • Manish Kumar
    • Skanda Dolphin
    • Wei-Ting Lai
    • Xingyu Chen
    • Angela Zhang
    • Zeinab Salehi
    • Zhifeng Tang
SELT Survey Results

This course introduces advanced theoretical and technical knowledge of digital circuits and embedded systems. Digital systems and embedded systems are at the heart of almost all modern mechatronics and electronics technologies, ranging from smartphones to autonomous vehicle technologies. This course will first focus on sequential logic circuits, also called finite-state-machine, by utilising field-programmable-gate-array boards and a hardware-description language. The second focus will be on embedded system design using a microprocessor and programming. Through the term projects, students will design working embedded systems, then critically analyse and evaluate the erformance of the systems. The course will also develop advanced cognitive, technical and communication skills to solve complex design problems.

Learning Outcomes

Upon successful completion, students will have the knowledge and skills to:

  1. Explain the fundamental principles of sequential digital circuits and finite state machines.
  2. Compare and describe the architecture and fundamental concepts of modern embedded microprocessor systems.
  3. Design complex digital systems using schematics and Verilog HDL, and implement these on commercial-grade field-programmable gate array (FPGA) development boards.
  4. Design an embedded system using C/C++ programming and microcontroller boards.
  5. Analyse critically, and evaluate the performance of systems against the design requirements.
  6. Plan, execute and report on a small project working in a group, communicating effectively in written form about their work.

Research-Led Teaching

The course will have guest lectures delivered by industry professionals. The projects will be modelled from real world applications and stretch the creativity of students.

Field Trips


Additional Course Costs


Required Resources

o Access to a Windows or Linux PC.

o Required software installed, where the software is free to download and use.

o An FPGA development board and a micro-controller board.

o Each student is provided an FPGA development board, which is not needed to return. The collection of FPGA development board will be advised later.

o Each student can borrow a micro-controller board from the School and needs to return this board after finishing the micro-controller project. The relevant details will be

provided later.

o Please contact the Co-Lecturers for any difficulties with accessing such resources.

o A lab notebook – An empty book with sufficient pages (e.g., 128 pages). Students should number each page (e.g., by hand).

o A recommended reading list is provided on the Wattle website.

o Students are encouraged to install the software for FPGA development and micro-controller development to assist with their learning, labs, and project work. Additional

information on recommended software will be made available on Wattle.

Staff Feedback

Students will be given feedback in the following forms in this course:

o Verbally, during lab activities where tutors make observations on students’ performance and progress.

o In writing, as response to their assignment/project submissions.

Student Feedback

ANU is committed to the demonstration of educational excellence and regularly seeks feedback from students. Students are encouraged to offer feedback directly to their Course Convener or through their College and Course representatives (if applicable). Feedback can also be provided to Course Conveners and teachers via the Student Experience of Learning & Teaching (SELT) feedback program. SELT surveys are confidential and also provide the Colleges and ANU Executive with opportunities to recognise excellent teaching, and opportunities for improvement.

Other Information

The IEEE citation style is required for references in the assignments of this course. Students are suggested to read the file named IEEE Citation Reference (which is uploaded into

the Wattle website) to know the requirements of this style, and pay special attention to correct citation format of books, conference articles, online sources, and periodicals. For

the sake of professionalism, the citation of non-publicised materials such as lecture slides is not suggested.

Important: Students often “appropriate” codes from external sources for their work without citation. Where students adopt external codes as part of their submitted work,

essential in-code referencing is required (see http://integrity.mit.edu/handbook/writing-code).

Students should remain mindful of the possible disciplinary consequences of poor referencing practices.

Class Schedule

Week/Session Summary of Activities Assessment
1 Lecture A: Course introduction & Combinational logic Lecture B: Inside FPGAs & Digital design flow Video Lecture 1: Non-ideal behaviour Video Lecture 2: Sequential logic
2 Lecture A: Latches & Flip-flops, Sequential design Lecture B: Verilog Video Lecture 3: Essential sequential designs Video Lecture 4: Introducing Verilog Tutorial 1 Lab 1: Introduction to Vivado
3 Lecture A: Extension session on Verilog Lecture B: Finite state machines Video Lecture 5: Verilog (continued) Video Lecture 6: Finite state machines Tutorial 2 Lab 2: Implementing designs onto FPGA and Essential sequential designs
4 Lecture A: Finite state machines design examples Lecture B: Practical suggestions, Wrap up of FPGA concepts Video Lecture 7: Practical aspects of design Video Lecture 8: RAM and ROM memories Tutorial 3 Lab 3: SSDs & Switch debouncers
5 Lecture A: Guest lecture from CEA Lecture B: Guest lecture from Xilinx or Intel Tutorial 4 Lab 4: Finite state machines
6 Lecture A: FPGA Project Drop-in session Lecture B: FPGA Project Drop-in session Lab 5: To be decided by CEA
7 Lecture A: General-purpose input/output (GPIO) and interrupts Lecture B: STM32: Timer Video Lecture 9: Introduction to micro-controllers Video Lecture 10: Review of C language (slides only) FPGA Project: Demo assessment FPGA Project: Report submission Lab 6: GPIO and interrupts
8 Lecture A: STM32: DMA and serial communication UART Lecture B: STM32: Serial communication I2C Tutorial 5 Lab 7: UART, Timer
9 Lecture A: STM32: Serial communication SPI Lecture B: STM32: Analog-to-digital converter (ADC) Tutorial 6 Lab 8: I2C
10 Lecture A: STM32: ADC DMA triggered by timer Lecture B: STM32: Real-time processing Micro-controller Project Drop-in sessions Tutorial 7 C Primer quiz
11 Lecture A: Micro-controller Project workflow Lecture B: No lecture Micro-controller Project Drop-in sessions Tutorial 8
12 Lecture A: Course wrap-up Lecture B: Guest lecture (TBD) Micro-controller Project: Demo assessment
13 Micro-controller Project: Report submission

Tutorial Registration

Please register Lab and Tutorial sessions via the MyTimetable system, by following the instructions on the Wattle website of ENGN4213/6213.

Assessment Summary

Assessment task Value Due Date Learning Outcomes
Practical Labs 26 % * 3, 4, 5
FPGA Project 25 % 21/04/2023 3, 5, 6
C Primer Quiz 4 % * 4
Micro-Controller Project 25 % 01/06/2023 2, 4, 5
Final Exam 20 % * 1, 2, 5

* If the Due Date and Return of Assessment date are blank, see the Assessment Tab for specific Assessment Task details


ANU has educational policies, procedures and guidelines , which are designed to ensure that staff and students are aware of the University’s academic standards, and implement them. Students are expected to have read the Academic Integrity Rule before the commencement of their course. Other key policies and guidelines include:

Assessment Requirements

The ANU is using Turnitin to enhance student citation and referencing techniques, and to assess assignment submissions as a component of the University's approach to managing Academic Integrity. For additional information regarding Turnitin please visit the Academic Skills website. In rare cases where online submission using Turnitin software is not technically possible; or where not using Turnitin software has been justified by the Course Convener and approved by the Associate Dean (Education) on the basis of the teaching model being employed; students shall submit assessment online via ‘Wattle’ outside of Turnitin, or failing that in hard copy, or through a combination of submission methods as approved by the Associate Dean (Education). The submission method is detailed below.

Moderation of Assessment

Marks that are allocated during Semester are to be considered provisional until formalised by the College examiners meeting at the end of each Semester. If appropriate, some moderation of marks might be applied prior to final results being released.

Assessment Task 1

Value: 26 %
Learning Outcomes: 3, 4, 5

Practical Labs

Practical labs in Semester 1 of 2023 will be running on campus. Thus, students are extremely expected to study this course on campus. Each student is required to

sign up her/his preferred lab session from Labs 1—4 in the MyTimetable system before the course starts.

Lab instruction sheets will be provided at least one week ahead, and students are encouraged to attempt the labs before attending lab sessions. Lab activities are

attached to a mark component. To obtain the marks, students must attend to their signed lab session and show their completed activities (e.g., the board and lab

notebook) before the end of the session.

Lab marks are awarded based on students’ completion of lab tasks, but not in response to assessment-style questions. Please note that a thorough read of lab

documents ahead of each session greatly assists students to successfully complete lab tasks.

Any working or notes related to the lab should be done on the “lab notebook”. It does not have to be neat but do not rip pages out of it – just cross it out. The lab

demonstrator might ask students to show their lab notebooks under certain circumstances.

Weight of all practical labs: 26% of the total mark for all practical labs, where each lab carries weighting of 2% – 4%.

Assessment Task 2

Value: 25 %
Due Date: 21/04/2023
Learning Outcomes: 3, 5, 6

FPGA Project

Students are required to independently develop an embedded solution using an FPGA development board. The project is conducted in groups of 2 students and involves

hands-on work using the board.

Rubric: An assessment criteria document will be made available on the Wattle website.

Weight: 25% of the total mark.

Assessment items: One written report from each group and hardware testing of submitted solution.

Assessment sessions of submitted solution: (i) 9am – 1pm on Monday 17 April, (ii) 3pm – 6pm on Monday 17 April, (iii) 9am – 10am on Tuesday 18 April, (iv) 12pm – 2pm

on Tuesday 18 April, and (v) 9am – 12pm on Wednesday 19 April. Session allocation among students will be determined by the Course Co-Conveners and Co-Lecturers at a later stage.

Report submission due and cut-off date: The due date is on Friday 21 April and the cut-off date is on Friday 28 April, where late submission penalty applies.

Individual Assessment: Group marks are moderated based on group members’ individual contributions. Students enrolled in ENGN6213 will need to complete an individual reflective question on top of the assignment workload.

Assessment Task 3

Value: 4 %
Learning Outcomes: 4

C Primer Quiz

Students are expected to work through a C Primer document with concepts and exercises over 5 weeks of the course. The exercises for each week are not graded.

Students will be able to complete a weekly online quiz on the Wattle website to self-evaluate their understanding. Quizzes are graded but not recorded in the student's

grade book. It is possible to take the quiz as many times as needed. You need a working knowledge of C Programming to complete micro-controller labs and project.

This assessment will be conducted in Weeks 9—10, where students need to attempt a final randomised multiple-choice quiz on the Wattle website. The questions in the final quiz are similar to those being asked during the 5-week self-learning.

?Weight: 4% of the total mark.

Assessment Task 4

Value: 25 %
Due Date: 01/06/2023
Learning Outcomes: 2, 4, 5

Micro-Controller Project

Students are required to independently develop an embedded solution using an ARM Cortex micro-controller board. The project can be conducted individually or a group

of 2 students, involving hands-on work using the board.

Rubric: An assessment description document will be made available on the Wattle website.

Weight: 25% of the total mark.

Assessment items: One written report from each group and hardware testing of submitted solution.

Assessment sessions of submitted solution: (i) 2pm – 5:30pm on Wednesday 24 May, (ii) 9am – 1pm on Thursday 25 May, (iii) 2pm – 5:30pm on Thursday 25 May, (iv)

9am – 12:30pm on Friday 26 May, and (v) 2pm – 5:30pm on Friday 26 May. Session allocation among students will be determined by the Course Co-Conveners and Co-Lecturers at a later stage.

Report submission due and cut-off date: The due date is on Thursday 1 June. There is no cut-off date.

Individual Assessment: Group marks are moderated based on group members’ individual contributions.

Assessment Task 5

Value: 20 %
Learning Outcomes: 1, 2, 5

Final Exam

A final exam featuring a mix of multiple-choice, short answer or extended answer questions will be held in the examination period. Students enrolled in ENGN6213 will have additional questions that are required for the students enrolled in ENGN4213. The aim of the final exam is to assess students’ theoretical concepts and understanding beyond the practical work.

Weight: 20% of the total mark.

Permitted materials: The following materials are allowed for the final exam (to be confirmed):

1. A scientific and non-programmable calculator.

2. One A4 page with notes on both sides, where both typed and hand-written notes are allowed.

3. A non-annotated dictionary for English as a Second Language (ESL) students, if needed.

Academic Integrity

Academic integrity is a core part of the ANU culture as a community of scholars. The University’s students are an integral part of that community. The academic integrity principle commits all students to engage in academic work in ways that are consistent with, and actively support, academic integrity, and to uphold this commitment by behaving honestly, responsibly and ethically, and with respect and fairness, in scholarly practice.

The University expects all staff and students to be familiar with the academic integrity principle, the Academic Integrity Rule 2021, the Policy: Student Academic Integrity and Procedure: Student Academic Integrity, and to uphold high standards of academic integrity to ensure the quality and value of our qualifications.

The Academic Integrity Rule 2021 is a legal document that the University uses to promote academic integrity, and manage breaches of the academic integrity principle. The Policy and Procedure support the Rule by outlining overarching principles, responsibilities and processes. The Academic Integrity Rule 2021 commences on 1 December 2021 and applies to courses commencing on or after that date, as well as to research conduct occurring on or after that date. Prior to this, the Academic Misconduct Rule 2015 applies.


The University commits to assisting all students to understand how to engage in academic work in ways that are consistent with, and actively support academic integrity. All coursework students must complete the online Academic Integrity Module (Epigeum), and Higher Degree Research (HDR) students are required to complete research integrity training. The Academic Integrity website provides information about services available to assist students with their assignments, examinations and other learning activities, as well as understanding and upholding academic integrity.

Online Submission

Assignments are submitted using Turnitin on the Wattle website. Students are required to electronically sign a declaration as part of the submission of assignments. Please keep a

copy of the assignment for students’ own records. Where applicable, assignments must include the cover sheet available on the Wattle website. Please keep a copy of tasks

completed for students’ own records.

Hardcopy Submission


Late Submission

Late submission of the FPGA project report without an extension are penalised at the rate of 5% of the possible marks available per 24 hour block or part thereof. Late submission of (i) the FPGA project report after the cut-off date and (ii) the micro-controller project report after the due date without an extension is not accepted.

Referencing Requirements

The Academic Skills website has information to assist you with your writing and assessments. The website includes information about Academic Integrity including referencing requirements for different disciplines. There is also information on Plagiarism and different ways to use source material.

Returning Assignments

Submitted assignments will be returned to students after marking either via the Wattle submission link or the Turnitin platform.

Extensions and Penalties

Extensions and late submission of assessment pieces are covered by the Student Assessment (Coursework) Policy and Procedure. Extensions may be granted for assessment pieces that are not examinations or take-home examinations. If you need an extension, you must request an extension in writing on or before the due date. If you have documented and appropriate medical evidence that demonstrates you were not able to request an extension on or before the due date, you may be able to request it after the due date.

Resubmission of Assignments


Privacy Notice

The ANU has made a number of third party, online, databases available for students to use. Use of each online database is conditional on student end users first agreeing to the database licensor’s terms of service and/or privacy policy. Students should read these carefully. In some cases student end users will be required to register an account with the database licensor and submit personal information, including their: first name; last name; ANU email address; and other information.
In cases where student end users are asked to submit ‘content’ to a database, such as an assignment or short answers, the database licensor may only use the student’s ‘content’ in accordance with the terms of service – including any (copyright) licence the student grants to the database licensor. Any personal information or content a student submits may be stored by the licensor, potentially offshore, and will be used to process the database service in accordance with the licensors terms of service and/or privacy policy.
If any student chooses not to agree to the database licensor’s terms of service or privacy policy, the student will not be able to access and use the database. In these circumstances students should contact their lecturer to enquire about alternative arrangements that are available.

Distribution of grades policy

Academic Quality Assurance Committee monitors the performance of students, including attrition, further study and employment rates and grade distribution, and College reports on quality assurance processes for assessment activities, including alignment with national and international disciplinary and interdisciplinary standards, as well as qualification type learning outcomes.

Since first semester 1994, ANU uses a grading scale for all courses. This grading scale is used by all academic areas of the University.

Support for students

The University offers students support through several different services. You may contact the services listed below directly or seek advice from your Course Convener, Student Administrators, or your College and Course representatives (if applicable).

AsPr Nan Yang

Research Interests

Signal Processing, Wireless Communications

AsPr Nan Yang

By Appointment

Research Interests


By Appointment
By Appointment
Hanwen Bi

Research Interests

Hanwen Bi

By Appointment
Dr Xiangyun Zhou
+61 2 6125 4054

Research Interests

Dr Xiangyun Zhou

By Appointment

Research Interests


By Appointment
Manish Kumar

Research Interests

Manish Kumar

By Appointment

Research Interests


By Appointment
By Appointment
Skanda Dolphin

Research Interests

Skanda Dolphin

By Appointment
Wei-Ting Lai

Research Interests

Wei-Ting Lai

By Appointment
Xingyu Chen

Research Interests

Xingyu Chen

By Appointment
Angela Zhang

Research Interests

Angela Zhang

By Appointment
Zeinab Salehi

Research Interests

Zeinab Salehi

By Appointment
Zhifeng Tang

Research Interests

Zhifeng Tang

By Appointment
Jiarui Wang

Research Interests

Jiarui Wang

By Appointment

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